1. Field of the Invention
The invention relates generally to the field of integrated circuit devices, and more specifically to protection arrangements for protecting the input circuit elements of the integrated circuit devices from excessive voltage levels. While the protection arrangements disclosed herein may be useful in any integrated circuit device, it is particularly useful in devices manufactured using manufacturing techniques for very large scale integration (VLSI) and ultra-large scale integration (ULSI) integrated circuit chips, and especially in those chips which have input circuit elements that are unable to withstand high input voltages which may result from electrostatic discharges which may occur at the terminal pins of the integrated circuit package while it is being handled.
2. Description of the Prior Art
Over the past twenty-plus years the design of integrated circuit devices has proceeded from small, medium and large scale integration to the current very large scale integration in an effort to incorporate more circuit elements such as transistors, capacitors and, to a lesser extent, resistors, onto a single chip, with the primary objects being to produce a smaller device that performs more functions and performs them faster. As a result, the circuit elements, especially the transistors, have not only become smaller in the amount of chip surface area which they take up, but they have also become thinner.
More specifically, in order to provide transistors with the desired increased switching speed, two things are done in the design of the transistors. First, since the transistors are generally MOSFETs (metal-oxide-semiconductor field effect transistors) or more generally IGFETs (insulated gate field effect transistors, where the gate electrode may be metal or any other suitable material). The source and drain regions are placed closer together to reduce the length of the channel and thus reduce the transit time of the charge carrier therethrough.
Second, the thickness of the insulating layer (for example, a silicon dioxide, or "oxide", layer) between the transistor's gate electrode, on the one hand, and the source and drain electrodes and the channel therebetween, on the other hand, is substantially reduced, which in turn reduces the input capacitance of the transistor, allowing it to react faster to a signal from upstream circuity. However, the reduction in the thickness of this "gate oxide" layer has resulted in a corresponding reduction in its ability to withstand abnormally high voltages without rupturing. Such high voltages can be particularly stressful on the gate oxide of input elements such as, for example, the first transistor in a circuit which receives a signal voltage from an input terminal. Such transistors can receive very high voltages from electrostatic discharge into the pins of the integrated circuit package during handling, which voltages can range up to the 5,000 volt level. In current VLSI devices, the thickness of the gate oxide layer has been reduced to the order of one to five hundred Angstroms, and so the breakdown voltage of the gate oxide in such transistors has been correspondingly reduced to the order of 10 to 50 volts. It is clear that 5000 volt electrostatic discharge voltages applied to input transistors having such a thin gate oxide would destroy them.
A number of input protection arrangements have been devised to protect the input transistors from excessively high input voltages. For example, resistors have been connected in series between the input terminal, or bonding pad (that is, the, generally metal, terminal on the chip surface to which is bonded the wire connecting to the circuit package pins) and the input transistor so as to attenuate the voltage as applied to the gate terminal of the input transistor. While this arrangement does reduce the voltage at the gate terminal of the input transistor, the addition of the resistor will also increase the capacitance of the path between the bonding pad and the processing circuitry on the chip, which will also reduce the circuit response of the chip. Furthermore, since a resistor impedes the flow of current away from the bonding pad, the bonding pad itself, as well as the oxide layer which insulates the pad from the substrate, may also be stressed. While the oxide layer under the bonding pad, which is a field oxide layer, is much thicker than the gate oxide layer (typically on the order of ten times the thickness of the gate oxide), an electrostatic discharge voltage can still cause ruptures in this field oxide if the current from the discharge is unable to dissipate sufficiently rapidly, which in turn can cause the metal from the pad to spike through to the substrate, thereby causing the chip to fail.
To supplement the resistors in input protection arrangements, diodes are often connected between the power buses, such as the V.sub.SS and V.sub.DD power lines on the chip, and the line connecting the bonding pad to the input transistor. These diodes discharge the excessive input voltage to the appropriate power line thereby serving as a clamp to limit the voltage level applied to the input circuit elements on the chip. The diodes can, however, also add capacitance to the input of the integrated circuit with the same problems noted above. Furthermore, the diodes are also subject to spiking through the doped region to the substrate, which can result in failure.
Other arrangements have used MOSFET or other insulated gate field effect (IGFET) input protection transistors in which the gate is formed over the thicker field oxide, not the thinner gate oxide, to ensure that they have a higher threshold, or turn-on, voltage. Typically the gate can be connected either to the input line or to a power bus. Currently-used input protection IGFETs, however, present significant problems. While such transistors have a relatively thick field oxide insulation over the channel region between the source and drain regions, the oxide is formed so as to taper to a somewhat thinner layer over the source and drain regions. Accordingly, while the thick oxide over the channel region may prevent the transistor from turning on until somewhat elevated signal voltage levels are reached, the thinner oxide between the source and drain regions, on the one hand, and the gate, on the other, may be ruptured as a result of voltage increases from electrostatic discharge, before a high voltage change can be discharged, thereby destroying the transistor. Furthermore, like diodes, the transistors are also subject to spiking through the doped source and drain regions, which can result in failure of the input protection circuit.